An advanced electronic design (chip) can have in excess of 40 blocks operating at different voltages referred to as voltage domains. Some voltage domains are completely independent of each other powered by independent supplies due to different standards or specifications, other voltage domains are powered by the same power source but the effective voltage reaching each domain is different due to voltage drop across the power delivery network caused by leakage during the idle state of one block or due to the dynamic power requirements of such a block during functional operation. Chip and system designers depend on EDA tools to estimate the effective voltage reaching each block as it has direct consequence on the operating speed of such a block.
One such power evaluation tool is PrimeRail® by SYNOPSYS®. PrimeRail® extracts the physical layout implementation of the power network of a chip and a mathematical abstraction (model) of the circuitry associated with it. It constructs an RC (resistance and capacitance) realization of the power network, and uses the current and voltage models of the associated circuitry driven by the power network to arrive at an estimation of the voltage drop (I*R drop) for each trunk or mesh starting at the power source and arriving at a block or at a particular point within a block. The voltage domain values for various blocks are then used in other EDA tools such as PrimeTime® by SYNPSYS® for timing closure analysis.
Such a power network analysis is subject to mathematical simplifications for compactness and efficiency as well as to the consideration of the process corners and to the accuracy of the current and voltage models of the powered circuitry in each block.